PCI Express

From TPU Reference

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PCI-Express is a technology based on the underlying concepts of the PCI bus interconnect.

It uses a layered design approach similar to the 7-layered OSI network topology which consists of:

Transaction Layer: Transmission of data requests/writes. These packet transmissions can be initiated on both the transmitter or the receiver side depending on who is requesting/writing data to what.
Data Link Layer: Regulates incoming and outgoing PCI-Express packets and also keeps track of them with a credit-based buffer system. The protocol of this layer relies on the common network packet protocols utilizing ACK/NAK sequencing for regulation.
Physical Link Layer: This layer is further broken down into two subcategories, the electrical link and the logical link.

The current version of the PCI-Express specification is 1.1 which allows for 16 full bi-directional differential lanes (hence the 16x). Each lane direction corresponds to roughly 500 MB/s of bandwidth (not including packet overhead) which gives a total of 8 GB/s of bi-directional bandwidth.

The next-generation of PCI-Express (2.0) will contain 32 full lanes.ItÃÂ´s expected to double actual 1.1 Bandwith.

WIP

The main difference between AGP and PCI-E is the bidirectional bandwidth which allows information to be sent both to and from the CPU.