SpeedStep

From TPU Reference

SpeedStep is an energy-efficiency management technology built into many Intel processors. It allows the clock speed of a processor to be dynamically changed based on CPU load, core temperature, and power source. SpeedStep can help to conserve battery power, extend processor life, and reduce noise from cooling. The power conservation to performance balance can also be adjusted manually by the user to best fit their needs.

Contents 1 What it does 2 SpeedStep revisions 3 Compatible processors 4 See also

What it does

While running a processor at high clock speeds allows for better performance, it also requires a higher core voltage which increases temperature and power consumption. Conversely, running a process at lower clock speeds decreases the needed core voltage, and thus decreases heat generation and power consumption. This is the main idea behind SpeedStep.

Since electrical resistance in processors generates heat, the less voltage being passed through a processor means less heat is produced. This is critical for notebook computers as their cooling systems are often required to be significantly smaller than their desktop counterparts, and therefore can dissipate less heat. A decrease in temperature means less discomfort for the user, increased device longevity (hard drives are very sensitive to heat), and system stability(processors begin to malfunction if they become too hot).

Another important consideration is the effect a decreased core speed and voltage has on power consumption. Since laptops and mobile devices run primarily on batteries, the decrease in power consumption by the processor at times of low load can significantly increase battery life.

SpeedStep revisions

• Version 1.1

First version of SpeedStep, found in Pentium III processors. It had two modes, low and high speed, where the clock multiplier of the process was decreased. The power consumption decreased by almost 75% when running in low.

• Version 2.1

Known as Enhanced SpeedStep, it is found in Pentium III-Mobile processors. This SpeedStep revision allows for a decrease in processor voltage during ‘’low speed’’ operation.

• Version 2.2

Simply Enhanced SpeedStep (V2.1) implemented for the Pentium 4-Mobile processor.

• Version 3.1

This revision was named EIST, and was implemented in the Banias core based Pentium M processors. While introducing an increased number of speed increments, can be adjusted by 100 MHz increments, it also allowed for the dynamic activation and deactivation of unused sections of a processors' L2 cache.

• Version 3.2

EIST implementation for dual core Intel mobile processors which feature shared L2 cache, known as Enhanced EIST.

Compatible processors

• Pentium III M
• Pentium 4 M
• Pentium M
• CoreDuo
• CoreSolo
• Core2Duo

See also

• Centrino
• PowerNow!